![]() Two Multichannel Buffered Serial Ports (McBSPs).Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability.Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations. ![]() 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane.Packet-Based DMA for Zero-Overhead Transfers.8192 Multipurpose Hardware Queues with Queue Manager.Memory Protection Unit for Both MSM SRAM and DDR3_EMIF.(Shared by Two DSP C66x CorePacs for C6657) Multicore Shared Memory Controller (MSMC).20 GFLOP per Core for Floating Point 1.25 GHz.40 GMAC per Core for Fixed Point 1.25 GHz.850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core.One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With.
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